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• 512 x 320 Element Sensor for Very Compact TV Cameras
• High Resolution
• Standard Interlaced 525-Line TV Output
• Ultra Low Blooming
• No Lag
• Precision Image Geometry
• No Microphonics
• Low Voltage and Power Requirements
• Small Size
• Highly Resistant to Image Burn-In
• Stable Sealed Silicon Gate Structure
• No Aliasing

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For further information or application assistance on this device, contact your RCA Sales Representative or write Charge-Coupled Device Marketing, Lancaster, PA 17604.

Developmental-type devices or materials are intended for engineering evaluation. The type designation and data are subject to change, unless otherwise arranged. No obligations are assumed for notice of change or future manufacture of these devices or materials.

Information furnished by RCA is believed to be accurate and reliable. However, no responsibility is assumed by RCA for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of RCA.
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The output register has the same 3-phase structure as the image and storage areas. The horizontal register receives one line of picture information from the storage area during each horizontal blanking interval (See Figure 3). The register contains 320 cells corresponding to each of the 320 columns in the image and storage areas plus two additional cells at the output.

Each line is clocked out at a 6.1 MHz picture element rate so that the 320 active elements are read out in the active line time of 52.7us. Typically the register is "over-clocked" by several pulses to provide a clean dark signal for video black level clamping. (Total number of pulses is approximately 335.) A bias charge is introduced into the input of the register and the signal is extracted by the output circuit.

Bias charge is introduced electrically into the input of the horizontal register by the IG1, IG2, and Ois connections. When these connections are operated as shown in Figure 3, a uniform low-noise bias charge (often referred to as "Fat Zero") is introduced into the output register to maximize the horizontal resolution. This circuit provides a constant amount of charge during each clock cycle. The amount of charge is determined primarily by the difference in voltage between IG1 and IG2.

It should be noted that a bias charge is required in the image and storage areas. This is provided by illuminating the image area with a uniform background light source (i.e., a couple of LEDs placed in a position to act as a uniform diffuse light source).
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The CCD signal is extracted from the horizontal register by the circuit shown in Figure 4. OOG is the last CCD gate in the horizontal register. The CCD signal charge is collected at the floating diffusion. This diffusion is reset to a positive potential once each clock cycle by RD and 0R. The voltage change on the floating diffusion is the signal which is sensed by the output transistor. The signal may be taken from OS as a source follower or from OD as an inverter.
For measurement purposes, the photocurrent delivered by the CCD in response to a light stimulus can be measured at the drain of the reset transistor — RD.
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Conditions: Standard EIA RS-170 525-line TV format operating at 25°C.